View HCA10014_90942.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HCA10014
Data Sheet August 1999 File Number
4769
15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output
HCA10014 op amp combines the advantage of both CMOS and bipolar transistors. Gate protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very high input impedance, very low input current, and exceptional speed performance. The use of PMOS transistors in the input stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute in single supply applications. A CMOS transistor pair, capable of swinging the output voltage to within 10mV of either supply voltage terminal (at very high values of load impedance), is employed as the output circuit. The HCA10014 operates at supply voltages ranging from 5V to 16V, (2.5V to 8V). It can be phase compensated with a single external capacitor, and have terminals for adjustment of offset voltage for applications requiring offset null capability. Terminal provisions are also made to permit strobing of the output stage.
Features
* MOSFET Input Stage Provides: - Very High ZI = 1.5T (1.5 x 1012) (Typ) - Very Low II 15V Operation. . . . . . . . . . . . . . . . . . . . . . . . . 5pA (Typ) 5V Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) * Ideal for Single Supply Applications * Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals can be Swung 0.5V Below Negative Supply Rail * CMOS Output Stage Permits Signal Swing to Either (or both) Supply Rails
Applications
* Ground Referenced Single Supply Amplifiers * Fast Sample and Hold Amplifiers * Long Duration Timers/Monostables * High Input Impedance Comparators (Ideal Interface with Digital CMOS) * High Input Impedance Wideband Amplifiers * Voltage Followers (e.g., Follower for Single Supply D/A Converter) * Voltage Regulators (Permits Control of Output Voltage Down to 0V)
Pinout
HCA10014 (SOIC) TOP VIEW
OFFSET NULL INV. INPUT NON-INV. INPUT V-
1 2 3 4 +
8 7 6 5
STROBE V+ OUTPUT OFFSET NULL
* Peak Detectors * Single Supply Full Wave Precision Rectifiers * Photo Diode Sensor Amplifiers
Ordering Information
PART NO. (BRAND) HCA10014 TEMP. RANGE (oC) -55 to 125 PACKAGE 8 Ld SOIC Tape and Reel PKG. NO. M8.15
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HCA10014
Absolute Maximum Ratings
DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . .16V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Metal Can Package) . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Input Offset Voltage
TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified SYMBOL |VIO| VIO/T |IIO| II AOL VS = 7.5V VS = 7.5V VO = 10VP-P, RL = 2k TEST CONDITIONS VS = 7.5V MIN 50 94 TYP 8 10 0.5 5 320 110 90 -0.5 to 12 32 13.3 0.002 15 0 22 20 10 2 MAX 15 30 50 10 320 0.01 0.01 45 45 15 3 UNITS mV V/oC pA pA kV/V dB dB V V/V V V V V mA mA mA mA
Input Offset Voltage Temperature Drift Input Offset Current Input Current Large Signal Voltage Gain
Common Mode Rejection Ratio Common Mode Input Voltage Range Power Supply Rejection Ratio Maximum Output Voltage
CMRR VICR VIO/VS VOM+ VOMVOM+ VOMVS = 7.5V RL = 2k RL = 2k RL = RL =
70 0 12 14.99 12 12 -
Maximum Output Current
IOM+ (Source) at VO = 0V IOM- (Sink) at VO = 15V
Supply Current
I+ I+
VO = 7.5V, RL = VO = 0V, RL =
2
HCA10014
Electrical Specifications
PARAMETER Input Offset Voltage Adjustment Range Input Resistance Input Capacitance Equivalent Input Noise Voltage Open Loop Unity Gain Crossover Frequency (for Unity Gain Stability 47pF Required) Slew Rate: Open Loop Closed Loop Transient Response: Rise Time Overshoot Settling Time (To <0.1%, VIN = 4VP-P) NOTE: 3. Although a 1M source is used for this test, the equivalent input noise remains constant for values of RS up to 10M. tr OS tS RI CI eN fT f = 1MHz BW = 0.2MHz, RS = 1M (Note 3) CC = 0 CC = 47pF SR CC = 0 CC = 56pF CC = 56pF, CL = 25pF, RL = 2k (Voltage Follower) 0.09 10 1.2 s % s 30 10 V/s V/s Typical Values Intended Only for Design Guidance, VSUPPLY = 7.5V, TA = 25oC Unless Otherwise Specified SYMBOL TEST CONDITIONS 10k Across Terminals 4 and 5 or 4 and 1 TYP 22 1.5 4.3 23 15 4 UNITS mV T pF V MHz MHz
3
HCA10014 Typical Performance Curves
150 LOAD RESISTANCE = 2k OPEN LOOP VOLTAGE GAIN (dB) OPEN LOOP VOLTAGE GAIN (dB) 140 130 120 110 100 90 80 -100 100 80 60 40 20 0 101 1 2 3 4 120 AOL SUPPLY VOLTAGE: V+ = 15V; V- = 0 TA = 25oC OL 4 3 2 -200 1 -300 -100
-50
0
50
100
102
103
TEMPERATURE (oC)
104 105 106 FREQUENCY (Hz)
107
108
1 - CL = 9pF, CC = 0pF, RL = 2 - CL = 30pF, CC = 15pF, RL = 2k
3 - CL = 30pF, CC = 47pF, RL = 2k 4 - CL = 30pF, CC = 150pF, RL = 2k
FIGURE 1. OPEN LOOP GAIN vs TEMPERATURE
17.5 12.5
FIGURE 2. OPEN LOOP RESPONSE
QUIESCENT SUPPLY CURRENT (mA)
QUIESCENT SUPPLY CURRENT (mA)
LOAD RESISTANCE = TA = 25oC OUTPUT VOLTAGE BALANCED = V+/2 V- = 0
14 12 10 8 6 4 2 0 OUTPUT VOLTAGE = V+/2 V- = 0 TA = -55oC 25oC 125oC
10
7.5
5 OUTPUT VOLTAGE HIGH = V+ OR LOW = V2.5
0 4 6 8 10 12 14 16 18 TOTAL SUPPLY VOLTAGE (V)
0
2
4
6
8
10
12
14
16
TOTAL SUPPLY VOLTAGE (V)
FIGURE 3. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
50 10
FIGURE 4. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
50 10
VOLTAGE DROP ACROSS PMOS OUTPUT STAGE TRANSISTOR (V)
VOLTAGE DROP ACROSS NMOS OUTPUT STAGE TRANSISTOR (V)
NEGATIVE SUPPLY VOLTAGE = 0V TA = 25oC POSITIVE SUPPLY VOLTAGE = 5V
10V
15V
NEGATIVE SUPPLY VOLTAGE = 0V TA = 25oC POSITIVE SUPPLY VOLTAGE = 5V
15V 10V
1
1
0.1
0.1
0.01
0.01
0.001 0.001
0.01
0.1
1.0
10
100
0.001 0.001
0.01
0.1
1
10
100
MAGNITUDE OF LOAD CURRENT (mA)
MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 5. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR (Q8) vs LOAD CURRENT
FIGURE 6. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR (Q12) vs LOAD CURRENT
4
OPEN LOOP PHASE (DEGREES)
HCA10014 Schematic Diagram
BIAS CIRCUIT CURRENT SOURCE FOR Q6 AND Q7 Q1 D1 Z1 8.3V R1 40k R 2 5k INPUT STAGE NON-INV. INPUT + INV.-INPUT 2 R3 1k Q9 Q10 Q11 R5 1k R6 1k R4 1k Q12 3 D5 D6 (NOTE 4) D7 D8 OUTPUT STAGE Q6 Q7 SECOND STAGE D2 D3 D4 Q4 Q5 Q2 "CURRENT SOURCE LOAD" FOR Q11 Q3 7 V+
Q8 OUTPUT 6
5
OFFSET NULL
1
COMPENSATION
8
STROBING
4
V-
NOTE: 4. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.
Application Information
Circuit Description
Figure 7 is a block diagram of the HCA10014. The input terminals may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the HCA10014 is ideal for single supply operation. Three Class A amplifier stages, having the individual gain capability and current consumption shown in Figure 7, provide the total gain of the HCA10014. A biasing circuit provides two potentials for common use in the first and second stages. Terminal 8 can be used both for phase compensation and to strobe the output stage into quiescence. When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supply rail potential at Terminal 7. This condition of essentially zero current drain in the output stage under the strobed "OFF" condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g., when the amplifier output is used to drive CMOS digital circuits in Comparator applications).
Input Stage
The circuit is shown in the schematic diagram. It consists of a differential input stage using PMOS field effect transistors (Q6, Q7) working into a mirror pair of bipolar transistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6. The mirror pair transistors also function as a differential to single ended converter to provide base drive to the second stage bipolar transistor (Q11). Offset nulling, when desired, can be effected by connecting a 100,000 potentiometer across Terminals 1 and 5 and the potentiometer slider arm to Terminal 4. Cascade connected PMOS transistors Q2, Q4 are the constant current source for the input stage. The biasing circuit for the constant current source is subsequently described. The small diodes D5
5
HCA10014
through D8 provide gate oxide protection against high voltage transients, including static electricity during handling for Q6 and Q7.
HCA10014 200A 1.35mA 200A 8mA (NOTE 5) 0mA (NOTE 6) V+ 7 BIAS CKT.
+ 3 INPUT 2 V4 5 1 CC COMPENSATION (WHEN REQUIRED) 8 STROBE AV 5X AV 6000X AV 30X OUTPUT 6
At total supply voltages somewhat less than 8.3V, zener diode Z1 becomes nonconductive and the potential, developed across series connected R1, D1 -D4, and Q1, varies directly with variations in supply voltage. Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in accordance with supply voltage variations. This variation results in deterioration of the power supply rejection ratio (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance.
Output Stage
The output stage consists of a drain loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance loads, the output can be swung within millivolts of either supply rail. Because the output stage is a drain loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail are shown in Figure 8. Typical op amp loads are readily driven by the output stage. Because large signal excursions are nonlinear, requiring feedback for good waveform reproduction, transient delays may be encountered. As a voltage follower, the amplifier can achieve 0.01% accuracy levels, including the negative supply rail.
NOTE: 7. For general information on the characteristics of CMOS transistor pairs in linear circuit applications, see Document # 619, data sheet on CA3600E "CMOS Transistor Array".
OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)
OFFSET NULL
NOTES: 5. Total supply voltage (for indicated voltage gains) = 15V with input terminals biased so that Terminal 6 potential is +7.5V above Terminal 4. 6. Total supply voltage (for indicated voltage gains) = 15V with output terminal driven to either supply rail. FIGURE 7. BLOCK DIAGRAM OF THE HCA10014
Second Stage
Most of the voltage gain is provided by the second amplifier stage, consisting of bipolar transistor Q11 and its cascade connected load resistance provided by PMOS transistors Q3 and Q5. The source of bias potentials for these PMOS transistors is subsequently described. Miller Effect compensation (roll off) is accomplished by simply connecting a small capacitor between Terminals 1 and 8. A 47pF capacitor provides sufficient compensation for stable unity gain operation in most applications.
17.5 15 12.5 1k 10 7.5 5 2.5 0 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 GATE VOLTAGE (TERMINALS 4 AND 8) (V) 500 SUPPLY VOLTAGE: V+ = 15, V- = 0V TA = 25oC LOAD RESISTANCE = 5k 2k
Bias Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R2 and zener diode Z1 serve to establish a voltage of 8.3V across the series connected circuit, consisting of resistor R1, diodes D1 through D4, and PMOS transistor Q1. A tap at the junction of resistor R1 and diode D4 provides a gate bias potential of about 4.5V for PMOS transistors Q4 and Q5 with respect to Terminal 7. A potential of about 2.2V is developed across diode connected PMOS transistor Q1 with respect to Terminal 7 to provide gate bias for PMOS transistors Q2 and Q3. It should be noted that Q1 is "mirror connected (see Note 7)" to both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to be identical, the approximately 200A current in Q1 establishes a similar current in Q2 and Q3 as constant current sources for both the first and second amplifier stages, respectively.
FIGURE 8. VOLTAGE TRANSFER CHARACTERISTICS OF CMOS OUTPUT STAGE
Input Current Variation with Common Mode Input Voltage
As shown in the Table of Electrical Specifications, the input current for the HCA10014 is typically 5pA at TA = 25oC when Terminals 2 and 3 are at a common mode potential of +7.5V with respect to negative supply Terminal 4. Figure 9 contains data showing the variation of input current as a function of
6
HCA10014
common mode input voltage at TA = 25oC. These data show that circuit designers can advantageously exploit these characteristics to design circuits which typically require an input current of less than 1pA, provided the common mode input voltage does not exceed 2V. As previously noted, the input current is essentially the result of the leakage current through the gate protection diodes in the input circuit and, therefore, a function of the applied voltage. Although the finite resistance of the glass terminal-to-case insulator of the metal can package also contributes an increment of leakage current, there are useful compensating factors.
10 4000 1000 INPUT CURRENT (pA) VS = 7.5V
100
10
1 TA = 25oC -80 -60 -40 -20 0 20 40 60 80 TEMPERATURE (oC) 100 120 140
INPUT VOLTAGE (V)
7.5
V+
15V TO 5V
FIGURE 10. INPUT CURRENT vs TEMPERATURE
7 5 PA 3 2.5 8 VIN 4 0V TO -10V V-1 0 1 2 3 4 5 6 INPUT CURRENT (pA) 7 2 6
Input Offset Voltage (VIO) Variation with DC Bias and Device Operating Life
It is well known that the characteristics of a MOSFET device can change slightly when a DC gate source bias potential is applied to the device for extended time periods. The magnitude of the change is increased at high temperatures. Users should be alert to the possible impacts of this effect if the application of the device involves extended operation at high temperatures with a significant differential DC bias voltage applied across Terminals 2 and 3. Figure 11 shows typical data pertinent to shifts in offset voltage encountered with devices during life testing. At lower temperatures (metal can and plastic), for example at 85oC, this change in voltage is considerably less. In typical linear applications where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. The 2VDC differential voltage example represents conditions when the amplifier output stage is "toggled", e.g., as in comparator applications.
7 OFFSET VOLTAGE SHIFT (mV) 6 5 4 3 2 1 0 0 500 1000 1500 2000 2500 TIME (HOURS) 3000 3500 4000 DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 0V OUTPUT VOLTAGE = V+ /2 DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 2V OUTPUT STAGE TOGGLED
0
FIGURE 9. INPUT CURRENT vs COMMON-MODE VOLTAGE
Offset Nulling
Offset voltage nulling is usually accomplished with a 100,000 potentiometer connected across Terminals 1 and 5 and with the potentiometer slider arm connected to Terminal 4. A fine offset null adjustment usually can be effected with the slider arm positioned in the midpoint of the potentiometer's total range.
Input Current Variation with Temperature
The input current of the HCA10014 circuit is typically 5pA at 25oC. The major portion of this input current is due to leakage current through the gate protective diodes in the input circuit. As with any semiconductor junction device, including op amps with a junction FET input stage, the leakage current approximately doubles for every 10oC increase in temperature. Figure 10 provides data on the typical variation of input bias current as a function of temperature.
FIGURE 11. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT vs OPERATING LIFE
7
HCA10014
V+ 7 3 + Q8 6 Q12 2 4 8 V8 RL 2 4 3 + Q8 6 Q12 RL 7 V+
FIGURE 12A. DUAL POWER SUPPLY OPERATION
FIGURE 12B. SINGLE POWER SUPPLY OPERATION
FIGURE 12. OUTPUT STAGE IN DUAL AND SINGLE POWER SUPPLY OPERATION
Power Supply Considerations
Because the HCA10014 is very useful in single supply applications, it is pertinent to review some considerations relating to power supply current consumption under both single and dual supply service. Figures 12A and 12B show connections for both dual and single supply operation. Dual Supply Operation - When the output voltage at Terminal 6 is 0V, the currents supplied by the two power supplies are equal. When the gate terminals of Q8 and Q12 are driven increasingly positive with respect to ground, current flow through Q12 (from the negative supply) to the load is increased and current flow through Q8 (from the positive supply) decreases correspondingly. When the gate terminals of Q8 and Q12 are driven increasingly negative with respect to ground, current flow through Q8 is increased and current flow through Q12 is decreased accordingly. Single Supply Operation - Initially, let it be assumed that the value of RL is very high (or disconnected), and that the input terminal bias (Terminals 2 and 3) is such that the output terminal (No. 6) voltage is at V+/2, i.e., the voltage drops across Q8 and Q12 are of equal magnitude. Figure 4 shows typical quiescent supply current vs supply voltage for the HCA10014 operated under these conditions. Since the output stage is operating as a Class A amplifier, the supply current will remain constant under dynamic operating conditions as long as the transistors are operated in the linear portion of their voltage transfer characteristics (see Figure 8). If either Q8 or Q12 are swung out of their linear regions toward cutoff (a nonlinear region), there will be a corresponding reduction in supply current. In the extreme case, e.g., with Terminal 8 swung down to ground potential (or tied to ground), NMOS transistor Q12 is completely cut off and the supply current to series connected transistors Q8, Q12 goes essentially to zero. The two preceding stages, however, continue to draw modest supply current (see the lower curve in Figure 4) even though the output stage is strobed off. Figure 12A shows a dual supply arrangement for the output stage that can also be strobed off, assuming
RL = by pulling the potential of Terminal 8 down to that of Terminal 4. Let it now be assumed that a load resistance of nominal value (e.g., 2k) is connected between Terminal 6 and ground in the circuit of Figure 12B. Let it be assumed again that the input terminal bias (Terminals 2 and 3) is such that the output terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q8 must now supply quiescent current to both RL and transistor Q12, it should be apparent that under these conditions the supply current must increase as an inverse function of the RL magnitude. Figure 5 shows the voltage drop across PMOS transistor Q8 as a function of load current at several supply voltages. Figure 8 shows the voltage transfer characteristics of the output stage for several values of load resistance.
Wideband Noise
From the standpoint of low noise performance considerations, the use of the HCA10014 is most advantageous in applications where the source resistance of the input signal is on the order of 1M or more. In this case, the total input referred noise voltage is typically only 23V when the test circuit amplifier of Figure 13 is operated at a total supply voltage of 15V. This value of total input referred noise remains essentially constant, even though the value of source resistance is raised by an order of magnitude. This characteristic is due to the fact that reactance of the input capacitance becomes a significant factor in shunting the source resistance. It should be noted, however, that for values of source resistance very much greater than 1M, the total noise voltage generated can be dominated by the thermal noise contributions of both the feedback and source resistors.
8
HCA10014
+7.5V
0.01F Rs 3 1M 2 4 8 1 0.01 F 30.1k + 6 7 NOISE VOLTAGE OUTPUT
The circuit uses an R/2R voltage ladder network, with the output potential obtained directly by terminating the ladder arms at either the positive or the negative power supply terminal. Each CD4007A contains three "inverters", each "inverter" functioning as a single pole double throw switch to terminate an arm of the R/2R network at either the positive or negative power supply terminal. The resistor ladder is an assembly of 1% tolerance metal oxide film resistors. The five arms requiring the highest accuracy are assembled with series and parallel combinations of 806,000 resistors from the same manufacturing lot. A single 15V supply provides a positive bus for the follower amplifier and feeds the CA3085 voltage regulator. A "scale-adjust" function is provided by the regulator output control, set to a nominal 10V level in this system. The line voltage regulation (approximately 0.2%) permits a 9-bit accuracy to be maintained with variations of several volts in the supply. The flexibility afforded by the CMOS building blocks simplifies the design of DAC systems tailored to particular needs.
47pF -7.5V BW (-3dB) = 200kHz TOTAL NOISE VOLTAGE (REFERRED TO INPUT) = 23V (TYP) 1k
FIGURE 13. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENTS
Typical Applications
Voltage Followers
Operational amplifiers with very high input resistances are particularly suited to service as voltage followers. Figure 14 shows the circuit of a classical voltage follower, together with pertinent waveforms in a split supply configuration. A voltage follower, operated from a single supply, is shown in Figure 15, together with related waveforms. This follower circuit is linear over a wide dynamic range, as illustrated by the reproduction of the output waveform in Figure 15A with input signal ramping. The waveforms in Figure 15B show that the follower does not lose its input to output phase sense, even though the input is being swung 7.5V below ground potential. This unique characteristic is an important attribute in both operational amplifier and comparator applications. Figure 15B also shows the manner in which the CMOS output stage permits the output signal to swing down to the negative supply rail potential (i.e., ground in the case shown). The digital-to-analog converter (DAC) circuit, described later, illustrates the practical use of the HCA10014 in a single supply voltage follower application.
Single Supply, Absolute Value, Ideal Full Wave Rectifier
An absolute value circuit is shown in Figure 17. During positive excursions, the input signal is fed through the feedback network directly to the output. Simultaneously, the positive excursion of the input signal also drives the output terminal (No. 6) of the inverting amplifier in a negative going excursion such that the 1N914 diode effectively disconnects the amplifier from the signal path. During a negative going excursion of the input signal, the HCA10014 functions as a normal inverting amplifier with a gain equal to -R2/R1. When the equality of the two equations shown in Figure 17 is satisfied, the full wave output is symmetrical.
Peak Detectors
Peak detector circuits are easily implemented, as illustrated in Figure 18 for both the peak positive and the peak negative circuit. It should be noted that with large signal inputs, the bandwidth of the peak negative circuit is much less than that of the peak positive circuit. The second stage of the HCA10014 limits the bandwidth in this case. Negative going output signal excursion requires a positive going signal excursion at the collector of transistor Q11, which is loaded by the intrinsic capacitance of the associated circuitry in this mode. On the other hand, during a negative going signal excursion at the collector of Q11, the transistor functions in an active "pull down" mode so that the intrinsic capacitance can be discharged more expeditiously.
9-Bit CMOS DAC
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC) is shown in Figure 16. This system combines the concepts of multiple switch CMOS lCs, a low cost ladder network of discrete metal oxide film resistors, a HCA10014 op amp connected as a follower, and an inexpensive monolithic regulator in a simple single power supply arrangement. An additional feature of the DAC is that it is readily interfaced with CMOS input logic, e.g., 10V logic levels are used in the circuit of Figure 16.
9
HCA10014
+7.5V 0.01F 7 3 10k 2 4 8 1 -7.5V CC = 56pF 2k 0.01F 25pF 2k + 6
BW (-3dB) = 4MHz SR = 10V/s
0.1F
Top Trace: Output Center Trace: Input FIGURE 14A. SMALL SIGNAL RESPONSE (50mV/DIV., 200ns/DIV.)
Top Trace: Output Signal; 2V/Div., 5s/Div. Center Trace: Difference Signal; 5mV/Div., 5s/Div. Bottom Trace: Input Signal; 2V/Div., 5s/Div. FIGURE 14B. INPUT OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME (MEASUREMENT MADE WITH TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)
FIGURE 14. SPLIT SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS
10
HCA10014
+15V
0.01F 3 10k 2 4 1 8 56pF 5 100k OFFSET ADJUST 2k + 7 6
0.1F
Top Trace: Output; 5V/Div., 200s/Div. Bottom Trace: Input Signal; 5V/Div., 200s/Div. FIGURE 15A. OUTPUT WAVEFORM WITH INPUT SIGNAL RAMPING (2V/DIV., 500s/DIV.) FIGURE 15B. OUTPUT WAVEFORM WITH GROUND REFERENCE SINEWAVE INPUT
FIGURE 15. SINGLE SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS. (e.g., FOR USE IN SINGLE SUPPLY D/A CONVERTER; SEE FIGURE 9 IN AN6080)
11
HCA10014
10V LOGIC INPUTS +10.010V LSB 9 6 14 11 2 CD4007A "SWITCHES" 9 13 7 8 4 806K 1% 5 402K 1% 200K 1% 1 12 8 100K 1% 806K 1% 5 13 1 12 806K 1% 806K 1% 750K 1% 806K 1% 13 8 (2) 806K 1% 1 12 5 (4) 806K 1% (8) 806K 1% CD4007A "SWITCHES" CD4007A "SWITCHES" MSB 1 10 BIT 1 2 3 4 5 6-9 REQUIRED RATIO MATCH STANDARD 0.1% 0.2% 0.4% 0.8% 1% ABS
8 3
7 10
6 6
5 3
4 10
3 6
2 3
NOTE: All resistances are in ohms.
806K 1%
PARALLELED RESISTORS +15V 10K
+15V
VOLTAGE REGULATOR 1 2 CA3085 3 6 7
62 OUTPUT +10.010V 8 22.1k 1% 1K REGULATED VOLTAGE ADJ LOAD 4 5 6
7 + HCA10014 1 8 100K OFFSET NULL 2K 56pF 3 VOLTAGE FOLLOWER 2
+ -
2F 25V
4 0.001F 3.83k 1%
0.1F
FIGURE 16. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND HCA10014
R2 2k R1 2 4k 3 HCA10014 + 5 1 8 20pF 100k OFFSET ADJUST R3 PEAK ADJUST 2k 0V 4 +15V 0.01 F 7 6 1N914 5.1k 0V
R2 R3 Gain = ------ = X = ------------------------------------R1 R1 + R2 + R3 X+X R 3 = R 1 ------------------ 1-X 0.75 R 3 = 4k ---------- = 6k 0.5 20VP-P Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V 1VP-P Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV
2
2K R 2 For X = 0.5: ----------- = -----4k R 1 Top Trace: Output Signal; 2V/Div. Bottom Trace: Input Signal; 10V/Div. Time base on both traces: 0.2ms/Div.
FIGURE 17. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
12
HCA10014
6VP-P INPUT; BW (-3dB) = 1.3MHz 0.3VP-P INPUT; BW (-3dB) = 240kHz 3 10k 7 + HCA10014 2 4 6 1N914 100 k 0.01F 2k -7.5V 2k -7.5V + 5F 0.01F +7.5V 0.01F +DC OUTPUT 10k 6VP-P INPUT; BW (-3dB) = 360kHz 0.3VP-P INPUT; BW (-3dB) = 320kHz 3 7 + HCA10014 2 4 6 1N914 100 k 5F + +7.5V 0.01F -DC OUTPUT
FIGURE 18A. PEAK POSITIVE DETECTOR CIRCUIT
FIGURE 18B. PEAK NEGATIVE DETECTOR CIRCUIT
FIGURE 18. PEAK DETECTOR CIRCUITS
3
CURRENT LIMIT ADJ + R2 1k
IC3 CA3086 10 Q4 11 + 390 9 8 7 Q3 6 1 3
1k Q5 12 Q1 4 5 20k 1k 56pF 5F 25V 1 25F 7 6 IC1 Q5 12 62k 14 13 R1 50k HCA10014 + 4 100k VOLTAGE ADJUST 8 2 3 30k ERROR AMPLIFIER OUTPUT 0 TO 13V AT 40mA + 13 14
Q2 2
0.01F
2.2k + 11 1, 2 Q4 5 Q3 6 Q2 4 Q1 3
IC2 +20V INPUT CA3086 10 9 8, 7
0.01F -
REGULATION (NO LOAD TO FULL LOAD): <0.01% INPUT REGULATION: 0.02%/V HUM AND NOISE OUTPUT: <25V UP TO 100kHz
FIGURE 19. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)
13
HCA10014
2N3055 + 2N2102 4.3k 1W 3.3k 1W 2N5294 + 1000pF 2.2k 1 IC2 CA3086 Q4 10, 11 1, 2 9 8, 7 3 5 Q1 6 Q5 12 14 13 Q4 5F + 8 2N2102 7 + HCA10014 IC1 4 8.2k 2 3 10k ERROR AMPLIFIER 43k + 100F Q1 Q3 Q2 1 + 10k 1k CURRENT LIMIT ADJUST
100F
+55V INPUT
OUTPUT: 0.1 TO 50V AT 1A
Q3 6 4
Q2
1k 62k -
50k VOLTAGE ADJUST -
REGULATION (NO LOAD TO FULL LOAD): <0.005% INPUT REGULATION: 0.01%/V HUM AND NOISE OUTPUT: <250VRMS UP TO 100kHz
FIGURE 20. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)
Error Amplifier in Regulated Power Supplies
The HCA10014 is an ideal choice for error amplifier service in regulated power supplies since it can function as an error amplifier when the regulated output voltage is required to approach zero. Figure 19 shows the schematic diagram of a 40mA power supply capable of providing regulated output voltage by continuous adjustment over the range from 0V to 13V. Q3 and Q4 in lC2 (a CA3086 transistor array lC) function as zeners to provide the supply voltage for comparator IC1. Q1, Q2, and Q5 in IC2 are configured as a low impedance, temperature compensated source of adjustable reference voltage for the error amplifier. Transistors Q1, Q2, Q3, and Q4 in lC3 (another CA3086 transistor array lC) are connected in parallel as the series pass element. Transistor Q5 in lC3 functions as a current limiting device by diverting base drive from the series pass transistors, in accordance with the adjustment of resistor R2. Figure 20 contains the schematic diagram of a regulated power supply capable of providing regulated output voltage by continuous adjustment over the range from 0.1V to 50V and currents up to 1A. The error amplifier (lC1) and circuitry associated with lC2 function as previously described, although the output of lC1 is boosted by a discrete transistor (Q4) to provide adequate base drive for the Darlington
connected series pass transistors Q1, Q2. Transistor Q3 functions in the previously described current limiting circuit.
Multivibrators
The exceptionally high input resistance presented by the HCA10014 is an attractive feature for multivibrator circuit design because it permits the use of timing circuits with high R/C ratios. The circuit diagram of a pulse generator (astable multivibrator), with provisions for independent control of the "on" and "off" periods, is shown in Figure 21. Resistors R1 and R2 are used to bias the HCA10014 to the midpoint of the supply voltage and R3 is the feedback resistor. The pulse repetition rate is selected by positioning S1 to the desired position and the rate remains essentially constant when the resistors which determine "on-period" and "off-period" are adjusted.
Function Generator
Figure 22 contains a schematic diagram of a function generator using the HCA10014 in the integrator and threshold detector functions. This circuit generates a triangular or square wave output that can be swept over a 1,000,000:1 range (0.1Hz to 100kHz) by means of a single control, R1. A voltage control input is also available for remote sweep control.
14
HCA10014
The heart of the frequency determining system is an operational transconductance amplifier (OTA) (see Note 9), lC1, operated as a voltage controlled current source. The output, IO, is a current applied directly to the integrating capacitor, C1, in the feedback loop of the integrator lC2, using a HCA10014, to provide the triangular wave output. Potentiometer R2 is used to adjust the circuit for slope symmetry of positive going and negative going signal excursions. Another HCA10014, IC3, is used as a controlled switch to set the excursion limits of the triangular output from the integrator circuit. Capacitor C2 is a "peaking adjustment" to optimize the high frequency square wave performance of the circuit. Potentiometer R3 is adjustable to perfect the "amplitude symmetry" of the square wave output signals. Output from the threshold detector is fed back via resistor R4 to the input of lC1 so as to toggle the current source from plus to minus in generating the linear triangular wave.
+15V
0.01F R1 100k ON-PERIOD ADJUST 1M 2k R3 100k 7 3 1F R2 100k 0.1F 0.01F 0.001F S1 + HCA10014 2 4 2k 6 OUTPUT OFF-PERIOD ADJUST 1M 2k
Frequency Range: Position of S1 0.001F 0.01F 0.1F 1F Pulse Period 4s to 1ms 40s to 10ms 0.4ms to 100ms 4ms to 1s
Operation with Output Stage Power Booster
The current sourcing and sinking capability of the HCA10014 output stage is easily supplemented to provide power boost capability. In the circuit of Figure 23, three CMOS transistor pairs in a single CA3600E (see Note 11) lC array are shown parallel connected with the output stage in the HCA10014. In the Class A mode of CA3600E shown, a typical device consumes 20mA of supply current at 15V operation. This arrangement boosts the current handling capability of the output stage by about 2.5X. The amplifier circuit in Figure 23 employs feedback to establish a closed loop gain of 48dB. The typical large signal bandwidth (-3dB) is 50kHz.
NOTE: 8. See Document # 619 (CA3600E) for technical information.
FIGURE 21. PULSE GENERATOR (ASTABLE MULTIVIBRATOR) WITH PROVISIONS FOR INDEPENDENT CONTROL OF "ON" AND "OFF" PERIODS
15
HCA10014
R4 270k VOLTAGE CONTROLLED CURRENT SOURCE +7.5V IC1 3 3k 3k 2 +7.5V R2 100k + 4 10M 5 -7.5V +7.5V SLOPE SYMMETRY 10k ADJUST VOLTAGE CONTROLLED INPUT R1 10k 22k 56pF FREQUENCY ADJUST (100kHz MAX) -7.5V 1 -7.5V 7 IO 6 CA3080A (NOTE 9) 3 2 IC2 HCA10014 + 4 8 6 39k 7 C2 3 INTEGRATOR C1 100pF +7.5V HIGH FREQ. ADJUST 3 - 30pF
THRESHOLD DETECTOR 150k +7.5V IC3 7 + 6
HCA10014 2 4 5 1 R3 100k
-7.5V
AMPLITUDE SYMMETRY ADJUST -7.5V
NOTE: 9. See Document # 475 (CA3080/CA3080A) and AN6668 for technical information. FIGURE 22. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)
+15V
0.01F 1M 1F CA3600E (NOTE 11) 7 3 2k INPUT 1F 4 2 + HCA10014 8 6 QP1
14
2
11
QP2
QP3
750k
13
1 500F
6
3
10
12 RL = 100 (PO = 150mW AT THD = 10%)
AV(CL) = 48dB LARGE SIGNAL BW (-3 dB) = 50kHz
8 QN1
5 QN2 QN3
7 510k
4
9
NOTES: 10. Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the HCA10014. 11. See Document # 619 (CA3600E). FIGURE 23. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE HCA10014
16
HCA10014 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
L
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
17

▲Up To Search▲

Price & Availability of HCA10014

	To Download HCA10014 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .